(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a metal oxide semiconductor field effect transistor (MOSFET) device on an insulator layer, featuring a strained channel.
(2) Description of Prior Art
In order to suppress short channel effects as the gate length of metal oxide semiconductor field effect transistor (MOSFET) devices are scaled down, higher body doping concentrations, thinner gate insulator layers, and shallower source/drain doping profiles are necessary. Such requirements have become difficult to meet when conventional device structures based on bulk silicon substrates are employed. The heavy channel doping required to provide adequate suppression of short channel effects result in degraded mobility and enhanced junction leakage. In addition the reduction of gate insulator thickness, to minimize short channel effects, leads to direct tunnelling gate leakage current as well as raising concerns regarding gate insulator reliability.
A method of suppressing short channel effects is the format ion of a MOSFET device featuring an ultra thin silicon layer as the channel region, located on an insulator structure. In this type of structure the source to drain current is restricted to flow only in the region close to the gate, in the ultra thin channel silicon layer, grown to a thickness typically less than 200 Angstroms. Since this configuration does not rely on a heavily doped channel region for suppression of short channel effects it avoids the problems of mobility degradation due to impurity scattering and threshold voltage fluctuation due to random variation of the number of dopant atoms in the channel region. As a ultra thin source/drain region would contribute high series resistance a raised source/drain structure can be employed to avoid the series resistance problem.
Performance optimization of an ultra thin body MOSFET device is possible through the use of a strained channel region, where the strain modifies the band structure of the channel region resulting in enhanced carrier transport properties. However the implementation of a MOSFET device on an insulator structure, featuring a strained channel region is difficult to achieve via conventional processes, and therefore not previously addressed. The present invention will however describe a novel fabrication process sequence is which a silicon channel region, under biaxial tensile strain, is successfully employed as a component for a MOSFET device, where the silicon channel region is located in a thin silicon layer which in turn is located on an insulator structure. Prior art such as: Kibbel et al, in U.S. Pat. No. 6,313,016; Liaw et al, in U.S. Pat. No. 5,891,769; Chu et al, in U.S. Pat. No. 5,906,951; Fitzgerald et al, in U.S. Pat. No. 6,291,321; and Leoues et al, in U.S. Pat. No. 5,659,187; have described methods of forming strained semiconductor and semiconductor alloys, on insulator structures. These prior arts however do not describe the novel process sequence used in this present invention, in which a thin, strained silicon layer is obtained on an underlying insulator structure.